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Instruction STR[B][T]
Function Store Register
Category Load and Store
ARM family All
Notes -


STR[B][T] : Store Register

The STR instruction permits you to store a 32 bit word (STR) or an unsigned byte (STRB) from a nominated register to a location in memory, in a variety of pre- and post-indexed addressing modes.

This operation is the logical opposite to Load Register, and as such most of the documentation here will refer to that instruction.

As with LDR, there are nine addressing modes:

  • Immediate offset
  • Register offset
  • Scaled register offset
  • Immediate pre-indexed
  • Register pre-indexed
  • Scaled register pre-indexed
  • Immediate post-indexed
  • Register post-indexed
  • Scaled register post-indexed

These are described in more detail below.

STR[B][T] is available in all versions of the ARM architecture. Later versions offer, additionally, STRH/STRSH to load unsigned or signed 16 bit halfwords, plus STRSB to load signed bytes. These instructions are available in architecture v4 or later (ARM8/StrongARM generation).


Many. Refer to the LDR instruction, and substitute STR for the LDR. Behaviour and actions are otherwise the same, except data is being placed into memory instead of being read from it.

By way of a quick recap:

  STR{cond}{B}     Rd, [Rn{, #{+|-}<12 bit offset>}]
  STR{cond}{B}     Rd, [Rn, {+|-}Rm]
  STR{cond}{B}     Rd, [Rn, {+|-}Rm, <shift> #<shift immediate>]
  STR{cond}{B}     Rd, [Rn #{+|-}<12 bit offset>]!
  STR{cond}{B}     Rd, [Rn, {+|-}Rm]!
  STR{cond}{B}     Rd, [Rn, {+|-}Rm, <shift> #<shift immediate>]!
  STR{cond}{B}{T}  Rd, [Rn], #{+|-}<12 bit offset>
  STR{cond}{B}{T}  Rd, [Rn], {+|-}Rm
  STR{cond}{B}{T}  Rd, [Rn], {+|-}Rm, <shift> #<shift immediate>


 Write words or bytes into memory, with optional write-back.

Addressing modes

Please refer to the LDR instruction for full details.


Simple I/O to memory transfer. In this example, R8 points to the I/O device base address, R9 points to the memory buffer where we will be writing our data, R10 points to the final address (in memory), and R11 is used as workspace. These values were chosen as they are banked in FIQ mode. The final note is the constant #DataWord which is an offset to the actual I/O register that we will be reading. The hardware clears the interrupt when the data is read.

  LDR     R11, [R8, #DataWord]  ; read word (fixed address)
  STR     R11, [R9], #4         ; write to memory (address updates)
  CMP     R9, R10               ; done?
  BLT     read                  ; no, go back for more


  • Immediate, Register, or Scaled register: Specifying PC as Rn uses the value of (the instruction + 8).
  • Pre-indexed (any) / Post-indexed (any): Specifying PC as either Rn or Rm is unpredictable.
  • Register or Scaled register (pre- or post- indexed): Using the same register as Rn and Rm is unpredictable.
  • Pre-indexed (any) / Post-indexed (any): Using the same register as Rd and Rn is unpredictable.
  • If Translation is used (post-indexed only), the registers used will be the User Mode registers, reardless of the currrent processor mode.
  • If a word write is not word aligned, the write may cause an alignment exception.
  • For byte writes, the least significant byte of the specified register is written.


The instruction bit patterns are described in the LDR documentation; an STR is indicated by the L bit being unset.

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