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Instruction TEQ
Function Test Equivalence
Category Data processing
ARM family All
Notes -


TEQ : Test Equivalence

The TEQ instruction allows you to test is two operands are equal. Unlike CMP, the V flag is not updated. The internal operation is a logical EOR of the two operands.
Operand 1 is a register, operand 2 may be a register, shifted register, or an immediate value (which may be shifted).

There is no S bit, it is implied. The N, Z, and C flags are updated as usual (N - result bit 31, Z if result zero, C is shifter carry out). V is not updated.

TEQ is important in conditional execution and decision making.

There is also a Test bits instruction for testing of specific bits are set or clear.


  TEQ  <op 1>, <op 2>


  <flags> = op_1 EOR op_2  ; result is not stored, only flags updated


  ; What sign is this value?
  ; If R1 < 0 Then R0 = -1 Else R0 = 1
  TEQ    R1, #0
  MVNMI  R0, #0
  MOVPL  R0, #1

While it may seem as if this behaves like CMP (and, indeed, replacing the TEQ in the example with CMP will behave the same way), this is not always true. For CMP does an addition internally, while TEQ performs an Exclusive OR.

TEQP in 26 bit modes

TEQP is used, in 26 bit modes, to write values to R15 status bits. For example, to disable interrupts (while preserving other registers), you would:

  MOV    R0, PC                    ; load current flags
  ORR    R0, R0, #(1<<26)+(1<<27)  ; set interrupt disable flags
  TEQP   R0, #0                    ; push flags into PC

Care must be taken not to access any banked registers (R8+) following the use of TEQP to change processor mode. It is usual to follow such a TEQP with a dummy instruction (MOV R0, R0) for this reason.

TEQP should NOT be used in 32 bit modes. Use [MSR] instead.


The instruction bit pattern is as follows:

31 - 28 27 26 25 24 - 21 20 19 - 16 15 - 12 11 - 0
condition 0 0 I 1 0 0 1 1 op_1 0 0 0 0 op_2/shift
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