32 bit rules

• Do not use:
  • TEQP
  • TSTP
  • CMPP
  • CMNP
  (non-P versions, ie CMP and TST are okay).
   
  
• Check instructions such as BIC and ORR which update PC, R14, or a register copied into PC.
  The trick of using ORRS PC, R14, #1<<28 won't work.
  In fact, do not use any instruction which writes to PC with the S bit set.
   
  
• Don't use R15 (PC) as the shift register in data processing operations.
   
  
• In LDR/STR, don't use PC as register offset and do not write back to it.
   
  
• In post-indexed LDR/STR, Rm and Rn must not be the same register. Likewise, for anything involving writeback, Rm and Rn should be different registers.
   
  
• LDM/STM, don't use the S bit in user mode. That means, don't use the '^' (ie LDMFD R13!, {PC}^).
   
  
• BL does not save the status register. This must be performed explicitly, but such code will not operate on ARM2 or ARM3 because they don't support the MRS/MSR instructions.
  Note, also, that it is NOT possible to see what the callee flags were, thus it does not make sense to restore flags that you don't know the status of. The best you can do is preserve the flags set on entry.

For those interested in what the S bit does in 32bit mode...

Any 32-bit write to R15 with the S bit set (MOVS, ORRS, TEQP, LDM...^) will transfer the SPSR for the current mode to the CPSR.
For example, assuming we are in irq_32 mode:

  MOVS PC, R14

This is not terribly useful as USR mode does not even have an SPSR!