B : Branch

  B<suffix>    <address>
B is the simplest branch. Upon encountering a B instruction, the ARM processor will jump immediately to the address given, and resume execution from there.
Note that the actual value stored in the branch instruction is an offset from the current value of R15; rather than an absolute address.

On other processors, you might often find code such as:

  OPT 1
  LDA &70
  CMP #0
  BEQ Zero
  STA &72
 .Zero RTS
(from the Acorn Electron User Guide issue 1 page 213)

On the ARM processor, that would become something like:

  OPT     1
  ADR     R1, #&70
  LDR     R0, [R1]
  CMP     #0
  BEQ     Zero
  STR     R0, [R1, #2]
  MOV     PC, R14
It isn't a very good example, but you can imagine how it would be better to execute conditionally instead of branching. On the other hand, if you have large sections of code there or if your code uses the status flags, you can implement all sorts of branching using conditional execution: Thus the single simple branch instruction can replace all of those branch and jump instructions present in other processors.
  OPT     1
  ADR     R1, #&70
  LDR     R0, [R1]
  CMP     R0, #0
  STRNE   R0, [R1, #2]
  MOV     PC, R14



BL : Branch with Link

  BL<suffix>   <address>
BL is another branch instruction. This time, register 14 is loaded with the contents of R15 just before the branch. You can reload R14 into R15 to return to the instruction after the branch - a primitive but powerful implementation of a subroutine.
This effect is quite well shown up in the screen loader 2 (example 4)...
      BL     switch_screen_mode
      BL     get_screen_info
      BL     load_palette

      MOV    R1, R5
      BL     read_byte
      CMP    R0, #255
      BLEQ   read_loop
      STRB   R0, [R2, #1]!
...where we can see three subroutines are called before the loader loop. Then, the read_byte subroutine is called in the loop, once under conditional execution.

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Copyright © 1999 Richard Murray