Instruction Set
(quick finder)
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Instruction Set(quick finder) |
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This is the 'shorter' quick finder, for programming under RISC OS. For a more complete look at the ARM instruction set, please refer to the complete quick finder document.
Instructions in bold are the core ARM instructions.
Instructions in italics are provided by the Floating Point Accelerator/Emulator.
| Instruction | Meaning | Earliest CPU / Comments
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| ABS | Absolute Value | Floating Point 1
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| ACS | Arc Cosine | Floating Point 5
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| ADC | Add with Carry | -
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| ADD | Add | -
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| ADF | Add | Floating Point 1 3
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| ADR | Get address of object (within 4K) | This is an assembler pseudo-instruction
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| ADRL | Get address of object (beyond 4K) | This is an assembler pseudo-instruction
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| ALIGN | Set the program counter to the next word boundary | This is an assembler pseudo-instruction
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| AND | Logical AND | -
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| ASL | Arithmetic Shift Left | This is an option, not an instruction
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| ASN | Arc Sine | Floating Point 5
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| ASR | Arithmetic Shift Right | This is an option, not an instruction.
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| ATN | Arc Tangent | Floating Point 5
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| B | Branch | -
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| BIC | Bit Clear | -
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| BL | Branch with Link | -
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| CDP | Co-processor data operation | -
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| CMF | Compare floating point value | Floating Point 1 3
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| CMN | Compare negated values | -
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| CMP | Compare values | -
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| CNF | Compare negated floating point values | Floating Point 1
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| COS | Cosine | Floating Point 5
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| DCx | Define byte (B), halfword (W), word (D), string (S), or floating point (F)
value. Some assemblers allow DCFS, DCFD, etc for FP precision. | This is an assembler pseudo-instruction
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| DVF | Divide | Floating Point 1 3
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| EOR | Exclusive-OR two values | -
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| EQUx | Define byte (B), halfword (W), word (D), string (S), or floating point (F)
value. Some assemblers allow EQUFS, EQUFD, etc for FP precision. | This is an assembler pseudo-instruction
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| EXP | Exponent | Floating Point 5
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| FDV | Fast Divide | Floating Point 1
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| FIX | Convert floating value to an integer | Floating Point 1 3
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| FLT | Convert integer to a floating value | Floating Point 1 3
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| FML | Fast multiply | Floating Point 1
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| FRD | Fast reverse divide | Floating Point 1
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| LDC | Load from memory to co-processor | -
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| LDF | Load floating point value | Floating Point 1 3
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| LDM | Load multiple registers | -
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| LDR | Load register (32 bit) | -
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| LDRB | Load byte (8 bit) into register | -
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| LDRH | Load halfword (16 bit) into register | StrongARM
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| LDRSB | Load signed byte (sign + 7 bit) into register | StrongARM
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| LDRSH | Load signed halfword (sign + 15 bit) into register | StrongARM
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| LFM | Load multiple floating point values | Floating Point 1
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| LGN | Logarithm to base e | Floating Point 5
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| LOG | Logarithm to base 10 | Floating Point 5
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| LSL | Logical Shift Left | This is an option, not an instruction; available on Thumb. |
| LSR | Logical Shift Right | This is an option, not an instruction; available on Thumb. |
| MCR | Co-processor register transfer (ARM to co-processor) | -
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| MLA | Multiply with Accumulate | -
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| MNF | Move negated | Floating Point 1
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| MOV | Move value/register into a register | -
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| MRC | Co-processor register transfer (co-processor to ARM) | -
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| MRS | Move status flags to a register | ARM 6
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| MSR | Move contents of a register to the status flags | ARM 6
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| MUF | Multiply | Floating Point 1 3
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| MUL | Multiply | -
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| MVF | Move value/float register into a float register | Floating Point 1 3
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| MVN | Move negated | -
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| NOP | No OPeration - usually outputs 'MOV R0, R0' | This is an assembler pseudo-instruction
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| NRM | Normalise | Floating Point 1
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| OPT | Select assembly options | This is an assembler pseudo-instruction
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| ORR | Logical OR | -
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| POL | Polar Angle | Floating Point 5
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| POW | Power | Floating Point 5
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| RDF | Reverse Divide | Floating Point 1
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| RFC | Read FP control register | Floating Point 1 4
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| RFS | Read FP status register | Floating Point 1 3
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| RMF | Remainder | Floating Point 2 3
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| RND | Round to integral value | Floating Point 2 3
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| ROR | Rotate Right | This is an option, not an instruction; available on Thumb. |
| RPW | Reverse Power | Floating Point 5
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| RRX | Rotate Right with extend | This is an option, not an instruction
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| RSB | Reverse Subtract | -
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| RSC | Reverse Subtract with Carry | -
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| RSF | Reverse Subtract | Floating Point 1
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| SBC | Subtract with Carry | -
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| SFM | Store Muliple Floating point values | Floating Point 1
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| SIN | Sine | Floating Point 5
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| SMULL | Signed Long (sign + 63 bit) Multiply | StrongARM
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| SQT | Square Root | Floating Point 2 3
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| STC | Co-processor data transfer | -
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| STF | Store floating point value | Floating Point 1 3
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| STM | Store multiple registers | -
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| STR | Store a register (32 bit) | -
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| STRB | Store a byte (8 bit) from a register | -
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| STRH | Store a halfword (16 bit) from a register | StrongARM
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| STRSB | Store a signed byte (sign + 7 bit) from a register | StrongARM
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| STRSH | Store a signed half-word (sign + 15 bit) from a register | StrongARM
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| SUB | Subtract | -
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| SUF | Subtract | Floating Point 1 3
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| SWI | Cause a SoftWare Interrupt | -
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| SWP | Swap register with memory | ARM 3
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| TAN | Tangent | Floating Point 5
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| TEQ | Test Equivalence (notional EOR) | -
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| TST | Test bits (notional AND) | -
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| UMLAL | Unsigned Long (64 bit) Multiply with Accumulate | StrongARM
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| UMULL | Unsigned Long (64 bit) Multiply | StrongARM
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| URD | Unnormalised round | Floating Point 1
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| WFC | Write FP control register | Floating Point 1 4
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| WFS | Write FP status register | Floating Point 1 3
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Instructions in bold are the core ARM instructions.
Instructions in italics are provided by the Floating Point Accelerator/Emulator.
Everything else are bits and pieces that were worth including, shift options and common assembler mnemonics...
Co-processor instructions are listed. However the ARM processors used in RISC OS machines do not support co-processors, and only the virtual co-processor functions present within the chip can be accessed. These provide facilities for setting up the ARM, cache, MMU, etc...